Logic Diagrams

This page contains the state diagram for our PLA controller, the state table that shows all of the outputs and inputs for each state, and the Meg file which is a text file used to generate the PLA layout.

The state diagram below is divided up into two phases: FIR Filter Phase and Update Weights Phase. NOTE that this diagram is not in the format of a standard state diagram: due to the large number of outputs, the inputs are on the transition lines and the outputs are beside the state. Thus, there are two states that are represented by more than one circle but are actually the same state with different outputs: Start Mult X*W and Start Mult X*E. There are 16 states total (4 state bits).

In the initial state (which is reached upon Restart), all of the latches and stack memory regions are cleared such that the system will be initialized properly. The first phase begins after initialization, the FIR filter phase or calculation of the filter output and error. This is done by multiplying the X and W vectors (requiring 8 multiplies) and then taking the difference between the desired signal input D and the sum of X*W, as shown below. Note that two counters are being used here as explained earlier, one to keep track of when a multiply operation has finished (COUNT9) and one to keep track of when the 8 multiply operations have been performed.

After the error has been obtained, there is a one clock cycle wait before the multiplication of X*E to update each weight can begin to insure that the multiply starts on CLKB2. Again, the counters are used to keep track of when each multiplication of X*E has finished and when all 8 multiplications for the 8 filter weights have been performed. Finally, the X stack must be rotated an additional time so that the new X that is loaded will replace the oldest one and another wait cycle is entered before starting the multiplication for the next iteration of the FIR Filter Phase.

The PLA State Table that contains the inputs necessary to transition to a state and the outputs from that state is shown below. Note that the Input Transition column presents the inputs that result in the PLA transitioning from the previous state to the current state. For multiple transitions to the same state from different states, the inputs required to transition for each previous state are listed and are separated by a blank space. The "Outputs Asserted" column matches up with the "Input Transition" column so that for each input the outputs are listed also separated by a blank space for each different sets of outputs. The "Next State" column simply lists the next state and what input conditions are necessary to reach that state.

State	Description	Input(s) Transition	Next State	Outputs Asserted
1	INIT (Clear all latches and stacks)	RESTART	Goto 2	CLRALL CLRACCUM
2	Load X & D Inputs, Start Multiply X*W, Clear Counters	None (From 1) COUNT9 (From 16)	Goto 3	STOREXD LOADMULT CLRCNT8 CLRCNT9
3	Rotate X & W Stacks, Send Cnt8A signal	None	Goto 4	ROTATEX ROTATEW CNT8A
4	Send Cnt8B signal to increment #multiplies X*W	None	Goto 5	CNT8B
5	Wait for Multiply X*W Completion	None	if COUNT9 then Goto 6 else Goto 5	(none)
6	Start Next Multiply X*W, Latch Accumulated Y	COUNT9 COUNT9 & COUNT8	if COUNT8 then Goto 7 else Goto 3	LOADMULT LACCUM CLRCNT9 LACCUM
7	Calculate E = D - Y (Send Subtract signal to the Adder)	COUNT8	Goto 8	MMULT SUBTRACT
8	Latch Error	None	Goto 9	MMULT SUBTRACT LERROR
9	Wait for CLKB2 before next Multiply	None	Goto 10	MMULT
10	Start Multiply X*E, Clear Counters	None (From state 9) COUNT9 (From state 14) COUNT9 & COUNT8 (From state 14)	if COUNT8 then Goto 15 else Goto 11	MWE MMULT LOADMULT CLRCNT8 CLRCNT9 CLRACCUM MDS MWE STOREW LOADMULT CLRCNT9 CLRACCUM MDS STOREW CLRACCUM
11	Get Weight for Add 1	None	Goto 12	MDS MMULT
12	Get Weight for Add 2, Rotate X & W, Latch Weight in Accum	None	Goto 13	MDS MMULT ROTATEX ROTATEW LACCUM CNT8A
13	Send Cnt8B signal to increment #multiplies X*E	None	Goto 14	MDS CNT8B
14	Wait for Multiply X*E Completion	None	if COUNT9 then Goto 10 else Goto 15	MDS
15	Rotate X Final	COUNT8 (From state 10) COUNT8 (From state 15)	if COUNT8 then Goto 15 else Goto 16	MDS CLRCNT9 ROTATEX CLRCNT8
16	Wait for Rotate X completion before Starting Next Iteration	None	if COUNT9 then Goto 2 else Goto 16	STOREXD LOADMULT CLRCNT8 CLRCNT9

Below is the input to Meg that is used to generate the PLA layout. Note that there are 16 states total (5 bits).

OUTPUTS: STOREXD STOREW ROTATEX ROTATEW MDS MWE MMULT LOADMULT CLRCNT8 CLRCNT9 CNT8A CNT8B SUBTRACT LACCUM LERROR CLRALL CLRACCUM;

GetWAdd2: -- second cycle of getting the weight (make sure adder output stable)

WaitBeforeMult2: -- wait for Rotate X completion before starting next multiply

State Diagram