The Deep Sub-Micron Challenge in High Speed Integrated Circuits

Yehia Massoud
Assistant Professor
ECE Department
Rice University

The continuous quest for higher performance has been pushing the VLSI technology towards ever decreasing feature sizes. With these feature sizes going deeper into the sub-micron regime, new effects have emerged as key to VLSI realization and have posed " The Deep Sub Micron challenge". This challenge has led to an urgent need and demand for accurate modeling, handling of deep sub-micron (DSM) effects. This talk addresses the Deep Sub-Micron challenge and the main problems introduced by the VLSI technology scaling, such as escalating power consumption, signal integrity, substrate coupling, inductive effects, and ringing power grid design.

For additional information, contact:

Yehia Massoud at massoud@rice.edu

Affiliates Meeting Agenda