Solutions to commonly encountered problems

Can't open layout in edit mode

There are two possible causes for this: either you do not have write permission to the file or you do not have a license. Cadence will allow you to open files in read-only mode without a license, but not in edit mode.

Try typing env at a unix prompt to make sure you have your license path set up correctly. After LM_LICENSE_FILE it should list /usr/site/cadence/licenses/license.ferr (if it has other paths as well, that's fine)

If that doesn't work, check to make sure that you have write permission on the file. To do this, type ls -al /home/user_name/your_cadence_directory/library_name/cell_name
The files permissions for this directory should be drwxr-xr-x, the single w signifies that only the owner of the file has write permission. If you are not the owner of the file, you will not be able to make any changes to the file.

DRC checking gives me an error about missing dio_id layer

This will happen if you don't create your library correctly. Try following the directions under Library more carefully, copy the directory containing your design into the new library, and try it again.
For more information on this see

How do I recover cellviews if icfb crashes?

Cadence keeps a temporary copy of the cellview that you are currently working on (called the panic cellview).  If cadence crashes, you can retrieve the panic cellview by typing dbOpenPanicCellView ("libname" "cellname" "viewname") in the CIW.  Here, libname is the library name, cellname is the name of your cellview, and viewname is either layout, schematic,...
Open your cellview after restoring the panic cell. 

DO NOT try to reopen the cellview before doing the dbOpenPanicCellView call or you've lost the panic cell.

Silicon Ensemble cell placement gives me the error:

** SE-USER-61 ERROR ** 14:30:50 * PLACE : * POWER/GROUND pin, inv1 gnd!, cannot appear in regular net gnd!

The first thing you must do is quit Silicon Ensemble. Once this error is loaded into the database it will keep appearing until the database is cleared. Now edit the def file to remove all power and ground nets and pins (with most standard cells they are routed automatically through abutment pins anyway). The PINS section is right after the COMPONENTS section of the file. To the right of the word "PINS" is listed the number of pins in the design. Decrease this by two and remove the first two pin declarations (vdd! and gnd!). The next section of the file is the NETS sections. vdd! and gnd! will again be listed as the first two nets. Decrese the net count by two, and remove all of the vdd! and gnd! net lists, including the lines USE POWER and USE GROUND. It is those two use declarations that caused the error: power and ground nets should not be routed as if they were regular nets. We will go back and route them by hand in Virtuoso when auto routing is done.