@INPROCEEDINGS{Wang:ISCAS2013:turbo_interleaver, 
author={Wang, Guohui and Vosoughi, Aida and Shen, Hao and Cavallaro, Joseph R and Guo, Yuanbin}, 
booktitle={IEEE International Symposium on Circuits and Systems (ISCAS)}, 
title={Parallel Interleaver Architecture with New Scheduling Scheme for High Throughput Configurable Turbo Decoder}, 
year={2013}, 
month={May}, 
pages={1340-1343}, 
keywords={decoding;parallel architectures;turbo codes;buffer structures;data rate requirement;hardware complexity reduction;high-throughput configurable turbo decoder;memory conflict problem;memory contention elimination;memory usage reduction;parallel interleaver architecture;parallel interleaving address generation hardware;scheduling scheme;wireless communication system;Clocks;Computer architecture;Decoding;Hardware;Parallel processing;Throughput;Writing;HSPA+;VLSI;contention-free;high throughput;memory conflict;parallel interleaver;parallel processing;turbo decoder}, 
doi={10.1109/ISCAS.2013.6572102}, 
ISSN={0271-4302},
}