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I have been involved in the VLSI design of the following chips at Rice University


Truncated On-line arithmetic based matched filter detector (2002) by Predrag Radosavljevic   Nils Bagge   Manik Gadhiok

Status: *Under Fabrication*
This chip was built as part of the VLSI class project in Fall 2002. The chip was based on a on-line arithmetic detection scheme developed at Rice.

http://www.owlnet.rice.edu/~nilz/elec422/

S. Rajagopal and J. R. Cavallaro, 'On-line arithmetic for detection in digital communication receivers', 15 th IEEE International Symposium on Computer Arithmetic, June 2001, Vail, CO. pp 257 -265 [PDF][Talk slides].

Detector:  Truncated online matched filter
Number of users supported: 1           
Area available: 3000x6000 inside the pad frame
Area used: ~90% (~15K transistors)
CMOS micron process: AMI 0.5 micron
Chip speed: waiting for fabrication ( execution time >= 10.11 ns expected)

 

 BLOCKS

Delay (ns)

# Transistors

Transient Power @ 5V (mW)

Half-adder

1.08

18

0.0281

Full-adder

3.01

38

0.0527

3-bit CLA

3.75

120

0.3286

Multiplier (non-pipelined)

22.53

2,062

3.6348

Multiplier (pipelined)

10.11

2,962

7.5790

On-line adder

6.72

394

0.5233

MS latch

-

18

0.1066

PLA

-

985

10.9040

Total (without padframe)

10.11 ns

15,229 transistors

43.4295 mW

Total (with padframe)

10.11 ns

19,917 transistors

-

Truncated conventional arithmetic based matched filter detector (2002) by Chad Cook Noah Deneau Richa Dubey Amy Lin

Status: *Under Fabrication*
This chip was built as part of the VLSI class project in Fall 2002. The chip was based on a detection scheme using truncated multipliers.

http://www.owlnet.rice.edu/~noahd/vlsi/

M. J. Shulte, J. E. Stine, J. E. Jansen, 'Reduced Power Dissipation Through Truncated Multiplication', IEEE Alessandro Volta Memorial Workshop on Low Power Design, March 1999, Como Italy pp 61-69

Detector: Truncated conventional matched filter
Number of users supported: 1          
Area available: 3000x3000 inside the pad frame
Area used: ~ 60% (due to I/O limitations)
CMOS micron process: 0.5 micron
Chip speed: waiting for fabrication

A bit-streaming pipelined multiuser detector (2000)  Laura Balzano   Andrew Dupre   Eric Furbish   Kevin Lynch

This chip was built as part of the VLSI class project in Fall 2000. The chip was based on a pipelined detection scheme developed at Rice. The group won the AMD-sponsored VLSI contest in 2000.

Project presentation of the group

S. Rajagopal and J. R. Cavallaro,'A bit-streaming pipelined multiuser detector for wireless communications', 2001 IEEE International Symposium on Circuits and Systems (ISCAS), May 2001, Sydney, Australia. vol 4. pp 128 -131 [PDF] [Talk slides]

Detector: Pipelined-Asynchronous-Multistage
Number of users supported: 4             
Area available: 3000x3000 inside the pad frame
Area used: ~85%
CMOS micron process: 0.5 micron
Chip speed: 2Mbps

A differencing multistage multiuser detector (1998) Gang Xu, Sridhar Rajagopal and Praful Kaul -

This chip was built as part of the VLSI class project in Fall 1998.

422 report 422 presentation

423 report 423 presentation

G. Xu, S. Rajagopal, J. R. Cavallaro, and B. Aazhang, 'VLSI implementation of the multistage detector for next generation wideband CDMA receivers', appearing in Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology: special issue on signal processing for wireless communications: algorithms, performance and architecture, vol.30, nos.1-3, March 2002, pp. 21-33. (invited paper)[PDF]

Detector: Differencing-Synchronous-Multistage
Number of users supported: 8
Area available: 2.2 x 2.2 mm2
Area used: 6000 Transistors
CMOS micron process: 1.2 micron
Chip speed: 190 Kbps/user, 1.52 Mbps aggregate

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