Contact Information:
Email:
ysun (at) rice (dot) edu
Address: Rice University, ECE Department
6100 Main St., MS 366
Houston, TX 77005
Basic Information:
I am a PhD student in the ECE
department at Rice
University. I currently work under the guidance of Dr.
Joseph R. Cavallaro as a member
of VLSI
Signal Processing group as well
as a member of Center
for Multimedia Communication (CMC) group.
I am currently studying aspects
of the physica layer baseband processing real-time hardware implementation for
the next generation wireless communications (3G/4G). I am currently focusing on
parallel algorithms and VLSI architectures for low-density parity-check (LDPC)
codes decoders, Turbo codes decoders, and MIMO demodulators. I am experienced in
ASIC/FPGA designs.
Research & Projects:
-
MIMO-OFDM PHY (physical)
layer design and implementation.
-
MIMO detector architecture
design for next generation wireless systems.
-
Low-density parity-check (LDPC)
decoder design for 4G wireless systems.
-
Turbo decoder design for
3GPP LTE and WiMAX
systems.
-
WARP
development: Wireless Open-Access Research Platform
-
High level C-to-RTL synthesis for DSP
algorithms.
-
Viterbi decoder design.
Publications:
(Google
Citation Link)
Journal Papers:
-
Y. Sun and J. R. Cavallaro, "Trellis-Search
Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture," IEEE Transactions on
Signal Processing, Vol 60, No 5, pp 2617 - 2627, May 2012.
-
Y. Sun and J. R. Cavallaro,
"High-Throughput Soft-Output MIMO Detector Based on Path-Preserving
Trellis-Search Algorithm," IEEE Transactions on
Very Large Scale Integration (VLSI), Vol
20, No 7, pp 1235 - 1247, July 2012.
-
Y. Sun and J. R. Cavallaro, "VLSI
Architecture for Layered Decoding
of QC-LDPC Codes With High Circulant Weight," IEEE Transactions on
Very Large Scale Integration (VLSI), 2012.
-
Y. Sun and J. R. Cavallaro,
“A Flexible LDPC/Turbo Decoder
Architecture,"
Journal of Signal Processing Systems.
Vol 64, No. 1, pp. 1-16, July,
2010.
-
Y. Sun and J. R. Cavallaro, “Efficient
Hardware Implementation of A Highly-Parallel 3GPP LTE, LTE-Advance Turbo
Decoder,"
Integration, the VLSI Journal,
Vol 44, No 4, pp 305-315, Sept. 2011.
-
M. Wu, Y. Sun, G. Wang, and J. R.
Cavallaro, “Implementation of a High Throughput 3GPP Turbo Decoder on GPU,” Journal of Signal Processing System, 2011.
-
M. Wu, Y. Sun, S. Gupta, and
J. R. Cavallaro, “Implementation of a High Throughput Soft MIMO Detector on
GPU,” Journal of Signal Processing System, Vol 64, No
1, July 2011.
-
M. Wu, C. Dick, Y. Sun, and
J. R. Cavallaro, “Low complexity scalable MIMO sphere detection
through antenna detection reordering,” Analog Integrated Circuits
and Signal Processing Journal, To appear.
Book Chapters:
-
Y. Sun, G. Wang, B. Yin, J. R. Cavallaro,
and T. Ly,
“High-Level
Design Tools for Complex DSP Applications,"
Expert Guide DSP for Embedded and Real-Time
Systems (in print).
-
Y. Sun,
K. Amiri, M. Brogioli, and J. R. Cavallaro,
“Application-Specific
Accelerators for Communications," Handbook on Signal Processing
Systems, Springer, pp. 329-362, 2010.
-
Y. Sun, J. R. Cavallaro, Y. Zhu, and M. Goel,
“Configurable and Scalable Turbo Decoder
Architecture for 4G Wireless Receivers," Fourth-Generation (4G) Wireless
Networks: Applications and Innovations,
IGI-Global, 2009.
Conference Papers:
-
Y. Sun,
Guohui Wang, and J. R. Cavallaro, "Multi-Layer Parallel Decoding Algorithm
and VLSI Architecture for Quasi-Cyclic LDPC Codes," in IEEE
International Symposium on Circuits and
Systems (ISCAS). pp. 1776 -
1779, May 2011.
-
Y. Sun
and J. R. Cavallaro, "Low-Complexity and High-Performance Soft MIMO
Detection based on Distributed M-Algorithm Through Trellis-Diagram," in IEEE International
conference on Acoustics, Speech and Signal Processing
(ICASSP). pp. 3398-3401, March 2010.
-
Y. Sun
and J. R. Cavallaro, "Scalable and Low Power LDPC Decoder Design Using High
Level Algorithmic Synthesis," in IEEE International System-on-Chip
(SoC) Conference (SOCC). pp. 267-270, Sept. 2009.
-
Y. Sun
and J. R. Cavallaro, “High Throughput VLSI Architecture for Soft-Output MIMO
Detection Based on a Greedy Graph Algorithm," in
ACM
Great Lakes Symposium on VLSI Design
(GLSVLSI). pp. 445-450, May 2009.
Best
Paper Award
-
Y. Sun
and J. R. Cavallaro, “Unified Decoder Architecture for LDPC/TURBO Codes,” in
IEEE Workshop on Signal Processing Systems (SiPS). pp. 13-18, Oct. 2008.
Best
Paper Award
-
Y. Sun
and J. R. Cavallaro, “A Low Power 1-Gbps Reconfigurable LDPC Decoder Design
for Multiple 4G Wireless Standards,” in IEEE International System-on-Chip
Conference
(SOCC). pp. 367-370. Sept. 2008.
Best
Paper Award
-
Y. Sun,
Y. Zhu, M. Goel and J. R. Cavallaro, “Configurable and Scalable High
Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards,”
in IEEE International Conference on Application-specific
System, Architectures and Processors (ASAP). pp. 209-214, July 2008.
-
Y. Sun, M. Karkooti and J. R. Cavallaro, “VLSI
Decoder Architecture for High Throughput, Variable Block-Size and
Multi-Rate LDPC Codes,” in IEEE International Symposium on
Circuits and Systems (ISCAS). pp. 2104-2107, May 2007.
-
Y. Sun, M. Karkooti and J. R. Cavallaro, “High
Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM
Systems,” in IEEE Dallas Circuits and Systems Workshop
(DCAS).
pp. 39-42, Oct 2006.
-
Y. Sun
and J. R. Cavallaro, “A New MIMO Detector Architecture Based on a
Forward-Backward Trellis Algorithm,” in IEEE 42nd Asilomar
Conference on Signals, Systems and Computers (ASILOMAR). pp.
1892-1896, Oct. 2008.
-
Y. Sun,
K. Amiri, J. R. Cavallaro, and Tai Ly, "Designing Scalable Wireless
Application-Specific Accelerators Using PICO High Level Synthesis," in
DesignCon 2010. Feb. 2010.
-
Y. Sun,
J. R. Cavallaro, and Tai Ly, "Low
power LDPC decoder created using high level synthesis," in EDA DesignLine.
Jan. 2010 (online
version).
-
G. Wang, Y. Sun, J. R.
Cavallaro and Y. Guo, "Concurrent Interleaver Architecture for High
Throughput Multi-standard Parallel Turbo Decoder," in IEEE
International Conference on Application-specific Systems, Architectures and
Processors (ASAP), pp. 113-121, September 2011.
-
G. Wang, M. Wu, Y. Sun, and J. R.
Cavallaro, "A Massively Parallel Implementation of LDPC Decoder on GPU," in
IEEE Symposium on Application Specific Processors. pp. 82-85, June 2011.
-
G. Wang, H. Shen, B. Yin, Y. Sun,
and Joseph R. Cavallaro, "High Performance Efficient Parallel Nonbinary LDPC
Decoding on GPU," in 2012 Asilomar Conference on Signals, Systems, and
Computers.
-
G. Wang, M. Wu, Y. Sun,
J. R. Cavallaro, “GPGPU Accelerated Scalable Parallel Decoding of LDPC
Codes,” in IEEE 45rd Asilomar
Conference on Signals, Systems and Computers. Nov. 2011.
-
M. Wu, C. Dick, Y. Sun, J. R.
Cavallaro "Improving MIMO Sphere Detection Through Antenna Detection Order
Scheduling," in Wireless Innovation Forum Conference on Communications
Technologies and Software Defined Radio. 2011.
-
M. Wu,
Y. Sun
and J. R. Cavallaro, “Implementation of a 3GPP LTE Turbo Decoder
Accelerator on GPU,” in IEEE Workshop on Signal Processing Systems (SiPS).
pp. 192-197. Oct. 2010.
-
O. Gustafsson, et al., Y. Sun,
et al., "Architectures
for cognitive radio testbeds and demonstrators - An overview,"
in IEEE International
Conference on Cognitive Radio Oriented Wireless Networks Communication,
pp. 1-6, June
9-11, 2010.
-
M. Wu,
Y. Sun
and J. R. Cavallaro, “Reconfigurable Real-time MIMO Detector on GPU,” in
IEEE 43rd Asilomar
Conference on Signals, Systems and Computers (ASILOMAR). pp. 690-694.
Oct. 2009.
-
M. Wu, S. Gupta,
Y. Sun
and J. R. Cavallaro, “A GPU Implementation of A Real-Time MIMO Detector,” in
IEEE Workshop on Signal Processing Systems (SiPS). pp. 303-308.
Nov. 2009.
-
G. Wang, B. Yin, K. Amiri, Y. Sun,
M. Wu, J. R. Cavallaro, “FPGA Prototyping of a High Data Rate LTE Uplink Baseband
Receiver,” in IEEE 43rd Asilomar
Conference on Signals, Systems and Computers (ASILOMAR). pp. 248-252. Nov. 2009.
-
M. Goel, J-F
Ren, Y. Zhu, S-J Lee and Y. Sun, “Forward Error
Correction Decoding for WiMAX and 3GPP LTE Modems,” in IEEE 42nd
Asilomar Conference on Signals, Systems and Computers (ASILOMAR). pp.
1143-1147, Oct. 2009. (Invited paper)
-
K. Amiri, Y. Sun, P. Murphy, C.
Hunter, J. R. Cavallaro and A. Sabharwal, “WARP, a Modular Testbed for
Configurable Wireless Network Research at Rice,” in IEEE Symposium for
Space Applications of Wireless & RFID, 2007, Houston, Texas, USA.
-
K. Amiri, Y. Sun, P. Murphy, C.
Hunter, J. R. Cavallaro and A. Sabharwal, “WARP, a Unified Wireless Network Testbed for Education and Research,” in
IEEE International Conference on Microelectronics Systems Education (MSE),
pp. 53-54. 2007.
Patents:
-
Y. Sun, J. R. Cavallaro, and J. Lilleberg
(Nokia). "Apparatus and Method
for Trellis-Based Detection in a Communication System,"
U.S. Patent Application. Filed
by Nokia on Oct. 14, 2010.
-
Y. Sun, Y. Zhu (TI), and M. Goel
(TI). "Scalable Decoder Architecture for Low Density Parity Check Codes,"
U.S. Patent Application. Filed
by Texas Instruments on Nov. 12, 2009.
-
J. Lilleberg (Nokia), Y. Sun, and J. R. Cavallaro. “Methods and Apparatus for MIMO Detection," U.S. Patent Application. Filed
by Nokia on June 1, 2009.
-
G. Wang, Y. Sun, J. R. Cavallaro,
and Y. Guo, "System and Method for Contention-Free Memory Access in an
Interleaver," U.S. Patent Application. Filed by Huawei on Nov, 2010
PhD Thesis:
Work Experience: