INPUTS: START HOLD RESTART OP3 OP2 OP1 OP0;
OUTPUTS: LOAD_OP LOAD_A LOAD_B
SUB ADDER_EN
ROT_L ROT_R SH_L SH_R SHIFT_EN
L_AND L_OR L_NOT LOGIC_EN
LOAD_OUT;
RESET ON RESTART TO S_INITIAL;
S_INITIAL: IF START THEN S_LOAD_OP(LOAD_OP)
ELSE S_INITIAL;
S_LOAD_OP: IF HOLD THEN S_LOAD_OP(LOAD_OP)
ELSE S_LOAD_A (LOAD_A);
S_LOAD_A: CASE (HOLD OP3 OP2 OP1 OP0)
1 ? ? ? ? => S_LOAD_A (LOAD_A);
0 0 0 0 0 => S_LOAD_B (LOAD_B);
0 0 0 0 1 => S_LOAD_B (LOAD_B);
0 0 1 0 ? => S_LOAD_B (LOAD_B);
0 0 1 1 0 => S_LOAD_OUTPUT(L_NOT);
0 1 0 0 0 => S_LOAD_OUTPUT(ROT_L);
0 1 0 0 1 => S_LOAD_OUTPUT(ROT_R);
0 1 0 1 0 => S_LOAD_OUTPUT(SH_L);
0 1 0 1 1 => S_LOAD_OUTPUT(SH_R);
ENDCASE => S_INITIAL;
S_LOAD_B: CASE (HOLD OP3 OP2 OP1 OP0)
1 ? ? ? ? => S_LOAD_B (LOAD_B);
0 0 0 0 0 => S_LOAD_OUTPUT;
0 0 0 0 1 => S_LOAD_OUTPUT(SUB);
0 0 1 0 0 => S_LOAD_OUTPUT(L_AND);
0 0 1 0 1 => S_LOAD_OUTPUT(L_OR);
ENDCASE => S_INITIAL;
S_LOAD_OUTPUT: CASE (HOLD OP3 OP2 OP1 OP0)
1 0 0 0 0 => S_LOAD_OUTPUT;
1 0 0 0 1 => S_LOAD_OUTPUT(SUB);
1 0 1 0 0 => S_LOAD_OUTPUT(L_AND);
1 0 1 0 1 => S_LOAD_OUTPUT(L_OR);
1 0 1 1 0 => S_LOAD_OUTPUT(L_NOT);
1 1 0 0 0 => S_LOAD_OUTPUT(ROT_L);
1 1 0 0 1 => S_LOAD_OUTPUT(ROT_R);
1 1 0 1 0 => S_LOAD_OUTPUT(SH_L);
1 1 0 1 1 => S_LOAD_OUTPUT(SH_R);
0 0 0 0 0 => S_INITIAL (ADDER_EN LOAD_OUT);
0 0 0 0 1 => S_INITIAL (ADDER_EN LOAD_OUT SUB);
0 0 1 ? ? => S_INITIAL (LOGIC_EN LOAD_OUT);
0 1 ? ? ? => S_INITIAL (SHIFT_EN LOAD_OUT);
ENDCASE => S_INITIAL;