WUGAZI

Table of Contents

Introduction

The Chip

• Cell Hierarchy
• Floorplan Layout of Chip
• Pin Assignment Listing
• 8-bit Register
• Chip Detail

Adder Unit

• Functional Description
• Basic Logic Diagram
• Carry Lookahead Logic Diagram
• Manchester Unit Logic Diagram
• Adder Unit Layout
• Detail of Manchester Section

Logic Unit

• Functional Description
• Basic Logic Diagram
• Logic Unit Layout
• Detail of Logic Cell

Shift Unit

• Functional Description
• Basic Logic Diagram (Top)
• Basic Logic Diagram (Bottom)
• Shift Unit Layout
• Detail of Shifter Cell

Control Unit

• PLA Description
• State Diagram Description
• State Diagram
• MEG Input Description
• Basic Logic Diagram
• Control Unit Layout

Multiplication Unit

• Functional Description
• Basic Logic Diagram of Product Cells
• Basic Logic Diagram of Multiplicand Cells
• Diagram of Multiplier Subunits
• Multiplication Unit Layout

Timing

• Timing Description
• Timing Signal Strengths
• Latch Clocking
• Timing Summary

Simulation and Testing

• Irsim Test Results: PLA
• Addition
• Subtraction
• OR
• Addition-OR
• AND
• NOT
• Rotate Left
• Rotate Right
• Shift Left
• Shift Right

Project Summary

• Division of Work
• References