The PLA unit controls the states and timing of our circuit. Currently, the PLA drives through five states. These states and their associated signals are described in greater detail below.
The important aspect of our PLA is how it dictates control signal strengths. All input signals to the PLA are minimum strength Va. The outputs directly from the PLA are all strength VbSa. Our PLA uses AND gates in the ANDBLOCK section of our CONTROL circuit in order to reduce the strength of certain timing critical control signals. These signals are described in greater detail in our timing documentation and diagram. Basically certain signals, such as those that control output to the buses, are reduced to strength Qa by and-ing the PLA signals with the A clock.
The Control unit initially also accounted for the multiplier control signals. In our final control unit, we do not include the multiplier signals since it is not part of our final design.