The timing of our ALU is centered around the inputted two-phase clock. Therefore, it is possible to analyze all our signals relative to the two clocks. Depending on the purpose of the signal, we alter its timing strength.
To start with, all our input registers are clocked with a load signal of strength Qa driving the master, and a Qb driving the slave. (See diagram). Thus, the value is maintained in the slave with continuous clock b and the input is only changed when the load signal is applied. Because of the strength of the load signal, the input must be of minimum strength Va. The outputs are definition VbSa, but in reality are valid as long as load is not applied.
In our functional units, the master latches are driven directly with clock a and the slave with clock b. Thus the input must be valid during Va. As a result, we do not need a separate load signal and can use clock a because we only need the output to be valid for one clock cycle where we latch it into the output register. Because the output is loaded onto a bus, we must prevents fights for the bus. Thus, output enable signal strength is of strength Qa, so that the output is only valid Qa.
Our output registers function in the same manner as our input registers.
As a side note, we will briefly discuss a design error that resulted in a minor disaster, and required for a redesign for many of the circuit components. In our first diagram, we had two signals into the registers, A and B. Unfortunately, we assumed NOT(a) = b and visa versa. This is not the case with a two phase clock. Therefore, we had to redo all of our master-slave latches in order to get four signals to them: a a_bar, b, and b_bar.