The logic unit takes two eight-bit numbers (A,B) and generates an 8-bit output that is the AND or OR of the two signals, or just the NOT of the first number A. The function that is outputted is based on the values of the control signals and_en, or_en, and not_en.
The inputs are stored into input latches which are controlled by clka and clkb as depicted in the Latch Clocking Document in the Timing section. The signals automatically propagate through all three logic units and generate A AND B, A OR B, and NOT A. Then, the signals are muxed into an output latch, and when the output is enabled, they are fed onto the output bus. The whole process requires two clock cycles and is relatively simple.
There were several other options in layout, from having separate logic segments for each function, to the combinational boolean unit described in the text. This unit allowed for more functions, but was much larger and would have made the NOT function quite difficult.