Who Are We?

Project Description
  • 50 Word Description
  • Functional Description
  • Scoring Algorithm
  • Pin Count
  • Pin Map

    Interactive Floor Plan
  • Old Block Diagrams

    Timing Diagrams
  • FSM Timing Diagram
  • Input Timing Diagram
  • Logic Timing Diagram
  • Output Timing Diagram

    FSM Design and MEG
  • FSM State Table
  • FSM Inputs and Outputs
  • FSM Magic Layout
  • FSM IRSIM

    Major Blocks & Subcells
  • Logic Diagram Links
  • Cell Hierarchy
  • Magic and IRSIM

    Performance Analysis
  • IRSIM
  • Spice

    Summary

     About Us
  • Mid-Semester Status Report

    • Group E Members:

  • Alexa Shoning
  • Hilary Scott
  • Ricky Radaelli-Sanchez

    Mid-Semester Status Report

    Our Mastermind project is steadily falling into place. We have completed:

    • functional description
    • pin count
    • block diagram
    • all of the logic and algorithm flows
    • design of the states of the main PLA
    • timing of the main PLA inputs and outputs
    • timing descrition of the entire chip

    We have already successfully overcome several hurdles. We are now fairly proficient in HTML for the webpage. We were able to significanly reduce the number of states and simplify timing by utilizing clock B. The design is completely solid and the timing is coming together. We have already divided up the magic layout duties of the various components, and those are all underway. In conclusion, our progress is good, but there is still much to do.

    • Last modified: Sat Oct 30 22:53:50 CDT 1999