FSM State Table

Project Description
  • 50 Word Description
  • Functional Description
  • Scoring Algorithm
  • Pin Count
  • Pin Map

    Interactive Floor Plan
  • Old Block Diagrams

    Timing Diagrams
  • FSM Timing Diagram
  • Input Timing Diagram
  • Logic Timing Diagram
  • Output Timing Diagram

    FSM Design and MEG
  • FSM State Table
  • FSM Inputs and Outputs
  • FSM Magic Layout
  • FSM IRSIM

    Major Blocks & Subcells
  • Logic Diagram Links
  • Cell Hierarchy
  • Magic and IRSIM

    Performance Analysis
  • IRSIM
  • Spice

    Summary

    About Us
  • Mid-Semester Status Report
  • FSM States
    State Description Inputs Asserted Timing Next State Outputs Asserted Timing
    A
    reset output temps, latching key, reset GC enterK VA1 if enterK then goto B


    ....
    else loop
    reset0
    resetGC
    latchK
    ....
    (none)
    VB1SA2
    VB1SA2
    VB1SA2 --> QA2
    ....
    (none)
    B
    reset B/W (none) (none) goto C resetBW VB2SA3
    C
    latching guess, incremeting GC enterG VA3 if enterG then goto D





    ....
    else loop
    latchG
    incrementGC
    latchGC
    shift0
    latchGBS
    resetV
    ....
    (none)
    VB3SA4 --> QA4
    VB3SA4
    VB3SA4 --> QA4
    VB3SA4 --> VA4SB4
    VB3SA4 --> VA4SB4 --> QB4
    VB3SA4
    ....
    (none)
    D
    latch comparator outputs, shift barrel shifters (none) (none) goto E latchC
    shift1
    latchVBS
    latchGBS
    VB4SA5 --> QA5
    VB4SA5 --> VA5SB5
    VB4SA5 --> VA5SB5 --> QB5
    VB4SA5 --> VA5SB5 --> QB5
    E
    latch black, latch comparator outputs, shift barrel shifter (none) (none) goto F latchB
    latchC
    shift2
    latchVBS
    latchGBS
    VB5SA6 --> QA6
    VB5SA6 --> QA6
    VB5SA6 --> VA6SB6
    VB5SA6 --> VA6SB6 --> QB6
    VB5SA6 --> VA6SB6 --> QB6
    F
    latch white, latch comparator outputs, shift barrel shifters S2
    S1
    S0
    VB5SA6
    VB5SA6
    VB5SA6
    if S2&S1'&S0' the goto K
    ....
    else goto G




    latch0
    ....
    latchW
    latchC
    shift3
    latchVBS
    latchGBS
    VB6SA7
    ....
    VB6SA7 --> QA7
    VB6SA7 --> QA7
    VB6SA7 --> VA7SB7
    VB6SA7 --> VA7SB7 --> QB7
    VB6SA7 --> VA7SB7 --> QB7
    G
    latch white, latch comparator outputs (none) (none) goto H latchW
    latchC
    VB7SA8 --> QA8
    VB7SA8 --> QA8
    H
    latch white (none) (none) goto I latchW VB8SA9 --> QA9
    I
    latch output temps GC0
    GC1
    GC2
    VA4SB4
    VA4SB4
    VA4SB4
    if GC2&GC1&GC0 then goto J
    ....
    else Goto B
    latchO
    ....
    latchO
    VB9SA10 -->QA10
    ....
    VB9SA10 -->QA10
    J
    you lose (none) (none) goto A WLK0 VB10SA11
    K
    you win (none) (none) goto A WLK1
    WLK0
    latchLS
    VB10SA11
    VB10SA11
    VB10SA11 --> QA11


    Last modified: Sat Oct 30 21:37:15 CDT 1999