FSM Inputs and Outputs

Project Description 50 Word Description Functional Description Scoring Algorithm Pin Count Pin Map Interactive Floor Plan Old Block Diagrams Timing Diagrams FSM Timing Diagram Input Timing Diagram Logic Timing Diagram Output Timing Diagram FSM Design and MEG FSM State Table FSM Inputs and Outputs FSM Magic Layout FSM IRSIM Major Blocks & Subcells Logic Diagram Links Cell Hierarchy Magic and IRSIM Performance Analysis IRSIM Spice Summary About Us Mid-Semester Status Report

FSM Outputs FSM Output Destination latchK 8-bit key latch latchG 8-bit guess latch incrementGC guess counter latchGBS 2 4-bit guess barrel shifters latchVBS 2 4-bit valid latches shift0,shift1,shift2,shift3 3 4-bit guess barrel shifters latchB 3-bit black score latch latchW 3-bit white score latch latchC 4-bit comparison latch latchLS low score latch resetBW b_latch, w_latch resetGC guess counter latchO 2 8-bit output latches latchGC guess counter resetV both 4-bit valid latches resetO 2 8-bit output latches WLK0,WLK1 win, lose, keep guessing output pin-0 and pin-1 respectively FSM Inputs FSM Inputs From S2,S1,S0 score latch GC2,GC1,GC0 guess counter RESTART input pin enterG input pin enterK input pin