Design Work
We have fully tested our chip, and we believe it is full functional. Our
spice performance analysis indicates that we will be able to run our
chip as fast as 67 MHz.
Possible Improvements
Currently, we plan to simulate the chip using vectors, which can not
realistically represent people. In order to allow people to play the game
in real time, we would need a more complex method of recogizing enter
signals from the user. We would have to take into account the fact that
a person depresses an enter button for much longer than a few nanoseconds.
Comments on CAD Tools
Magic was sufficient for our design needs. IRSIM was somewhat limited
in its ability to approximate the timing of FSM output signals and other
internal signals that were not strictly based on the clocks. Hspice does
not have any good documentation. Awaves is even worse.
Official Project Name: MSTRMND
This is a list of what each person individually contributed to the
project...
Hilary Scott
Wrote MEG description for the FSM
Wrote MEG description for the PLA Decoder
Comparison Logic Block (red box on diagram)
Routed core
Chip debugging
Alexa Shoning
Wrote MEG description of FSM
Input Logic Block (blue box on diagram)
Low Score Logic Block
Clock Buffering
Chip debugging
Ricky Radaelli-Sanchez
Score Logic: 3-Bit Adder and 3-Bit Counter
Output Logic: 8-Bit MUX
Routed I/O Pad
Web page design/maintenance
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